1. Field of the Invention
The present invention relates generally to an improved data processing system, and in particular to a computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores.
2. Description of the Related Art
With increasing processing demands, many data processing systems now contain multiple processors. With multiple processors, processing tasks may be split up between these processors. Further, these processors may access information that is accessed by other processors within the data processing system.
It is important for each processor in a multi-data processing system to be able to access updated values. At times, it is desirable to know when each processor has access to selected data. Instructions, such as a flush or invalidate instruction, imply that other processors will obtain updated values for information in memory. A flush instruction is an instruction that forces a flush of all changes to memory that are in a cache local to a central processing unit (CPU) into main memory. An invalidate instruction is an instruction that invalidates any cache lines that other CPUs may have that are for the same memory. For example, when data is written to a cache line for a first CPU, an invalidate signal may be sent onto the fabric to the other CPUs in the system which contain a cache line for the same memory. The invalidate signal causes all other CPUs that have the same cache line to flush the cache line to remove the stale value in their cache. After an invalidate instruction, other CPUs will load the updated value from memory, rather than a stale value from the cache. A sync instruction may also be used to ensure that all of the memory store operations have completed.
As discussed by Kevin M. Lepak and Mikko H. Lipasti in Temporally Silent Stores, ACM Digital Library, Oct. 2002, pp. 1-12. (hereinafter “Lepak”), the frequently occurring traditionally silent and temporally silent stores may be exploited to reduce memory traffic and improve performance. A traditionally silent store, or a simple silent store, is a store instruction that does not change the value already present at the target memory address. A temporally silent store is a store instruction that changes the value at the target memory address temporarily, and then changes it back to its original value. Traditionally silent stores and temporally silent store can occur frequently. As it has been demonstrated in research, memory addresses that have shown to exhibit temporally silent store behavior in the past tend toward this same behavior in the future (i.e., spin locks which always change the stored value between 0 and 1).